This invention relates generally to semiconductor integrated circuit devices and more particularly, it relates to a dual mode N-bit counter which may be used to count either up or down by one or two.
There are known in the prior art a number of counter circuits, but they tend to suffer from the disadvantage in that such counter circuits could either only count up or count down. Further, many of these prior art counters were formed of irregular structures which increased substantially the cost in design layout and manufacturing. In addition, these conventional counter circuits were quite complex since a relatively large number of components were used in their implementation and thus required the use of increased amounts of chip area, thereby adding to the expense of production.
It would therefore be desirable to provide a dual mode N-bit counter which can be used to count either up or down by one or two. It would be expedient to have such a dual mode N-bit counter contain a plurality of identical bit cells, each cell being formed with a smaller number of components than has been traditionally required. Further, it would also be expedient to construct each bit cell to be of a regular configuration or structure so as to conform to a repeatable pattern suitable for very large scale integration (VLSI) with high packing density.